/*
 * @Description  : testbench
 * @authorName   : GuoJi
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 13663585559@163.com
 * @version      : 1.0
 * @Date         : 2023-06-04 20:13:23
 * @LastEditTime : 2023-06-04 20:13:32
 */

`timescale 1ps / 1ps

module present_sram_tb;

reg  clk;
reg  start;
wire[63:0] result;

present_sram_top present_sram_top_u(
    .clk(clk),
    .start(start),
    .result(result)
);

initial
begin
    clk = 1'b0;
    forever #5 clk = ~clk;
end

initial
begin
  $readmemh("sram.txt",present_sram_top_u.sram_ctl_u.mem);  
  start <= 0;
  #10 start <= 1;
  #10 start <= 0;
  #500   start <= 1;
  #10    start <= 0; 
end

endmodule